1. Field of the Invention
The present invention generally relates to a package method for electronic components by a thin substrate, and more particularly to a wafer level package method of a ultra thin, high density package substrate employed for the complicated package multiple components integration.
2. Description of Prior Art
With rapid development of the integration of IC chips chasing after the Moore's Law, the relevant package skill has reached the unprecedented and innovative level than ever. In numerous innovative package skills, the WLP (Wafer Level Packaging) or CSP (Chip Scale Package) is one of the IC chip package and is also the most representative skill which is considered as a revolutionary skill. The biggest difference from the arts prior thereto is: the concept of the wafer level packaging is directly implemented on the silicon wafer to finish the package process of the integrated circuit rather than packaging respective IC chips after dicing the silicon wafer as previously implements in traditional package process. After the wafer level packaging, the sizes of the IC chips is almost the same as the original size of dies. Therefore, it is also well known as WLCSP (Wafer Level Chip Scale Package).
However, the size of the present WLP restricts the Fan-out area of the layout. Fan-out WLP is developed accordingly. For example, the eWLB (Embedded wafer level ball grid array) skill of Infinion, the SiWLP (System in Wafer-Level Package) or the SMAFTI (SMArt chip connection with Feed-Through Interposer) skill of Renasas can be illustrated.
Please refer to FIG. 1A to FIG. 1F which depict schematic diagrams of a wafer level package according to prior arts. The aforementioned Fan-out WLP in the field does not have any standard process. Kinds of relevant skills may slightly differ from each other but the basic skill concept is almost the same.
As shown in FIG, 1A, a temporary carrier 100 is provided. The temporary carrier 100 can be a silicon wafer in a wafer level package.
As shown in FIG. 1B, multiple layers which are formed on the temporary carrier 100 comprises lines of metal layers 102, 106 and dielectric layer 104. After the metal layers 102, 106 and the dielectric layer 104 are manufactured, the multi layers (i.e. the multi-layer substrate for packaging the IC chip) are completed. Only portion of the multi-layer substrate is shown in FIG. 1B for simplification. Practically, 3-5 layers or more can be formed.
As shown in FIG. 1C, several pad layers (ball pad layers) 108 are formed on the surface of the multi-layer substrate. The pad layers 108 are connected with the metal layer 106 thereunder with the via metals 110 as shown in FIG. 1C.
As shown in FIG. 1D, the packages 112 are performed to the chip (bare die) 150 through the pad layers 108. The method of packages 112 can be well known Flip chip bump bonding MBB (micro bump bonding) or SMT BGA (Surface Mount Ball Grid Array) for illustrations.
As shown in FIG. 1E, then, molding 152 is performed to the bonded chips.
As shown in FIG. 1F, the BGA ball mounting 114 is performed to bottom surface of the multi-layer substrate the after the molded chip 150 and the multi-layer substrate is parted from the temporary carrier 100.
The WLP as aforementioned is merely simple description but the basic concept of the WLP is to manufacture the multi-layer substrate on the silicon wafer 100 and to package the chip 150. After the multi-layer substrate is parted from the temporary carrier 100, then the dice or singulation process is implemented to finish the package of the respective IC chip 150. However, the yield of the entire package process depends on the sum of the yields of respective components. For the WLP as aforementioned, the dice or singulation process cannot implement until the wafer molding to the whole silicon wafer is finished. Unavoidably, the defect in the multi-layer substrate can cause some individual IC chip failure but the IC chips with qualified package still cannot be selected until the dice or singulation process is done.
Moreover, the SMAFTI package method proposed by Renasas is utilized for packaging a memory chip with a SoC (System-On-a-Chip) or a logic chip as illustration.
First, manufacturing multiple layers (FTI, Feed-Through Interposer), i.e. an    intermediate layer on a silicon wafer;    Implementing bonding to the memory chip;    performing a wafer molding to the whole wafer;    removing the silicon wafer;    implementing bonding to the SoC (System-On-a-Chip) or the logic chip through the FTI (Feed-Through Interposer). The package completed product (the packaged memory chip with the SoC or the logic chip) are connected to an external system circuit board (PCB) with a BGA.
The yield of the entire package process depends on the sum of the yields of respective components. In the foregoing case, that is: the yields of 1. the manufacture of the FTI (Feed-Through Interposer); 2. memory chip package; 3. the SoC package or the logic chip package.
In the aforesaid SMAFTI, the yield of the FTI (Feed-Through Interposer) is a major factor to affect the yield of the entire package process. Even a test is performed to the FTI (Feed-Through Interposer) in advance. The wafer molding cannot allow selectively implementing bonding or molding to individual IC chip. It obstructs the yield improvement of the entire package process and especially the main reason to increase the pointless manufacture material cost.
Moreover, the aforesaid WLP skill is limited to perform flip chip bonding to one kind of bare die. In this field, there is no total solution specifically proposed for a thin and flexible multi-layer substrate of integrally packaging multiple elements. Beside, in the aforesaid WLP, the multi-layer substrate is used for packaging the SoC or the logic chip first. Then, another side of the chip which is connected with a ball grid array is employed to connect the external system circuit (PCB) and the whole package process is finished thereby. Under the condition that the complexity and integration of the package process becomes higher, the package processes utilizing a flexible multi-layer substrate are constantly developed and reveals more possibility of the development related with the package process. It is has been considered as the package skill in the next generation. Once the foregoing concept of wafer level package according to prior arts remains to be adopted, the drawbacks of impossibility for performing pre test to the FTI (Feed-Through Interposer) still exist consequently. The complete test cannot be realized accordingly. The benefits of the wafer level package process utilizing a flexible multi-layer substrate for integrally packaging multiple elements cannot but conducted and the package yield which is desperate for improvement in the prior arts cannot be eliminated and lasts.
Consequently, there is a need to develop a total solution for the package process of a thin substrate which is specific for the test, the packages, the molding and respective processes for completing the final products and to provide a package method and a test method of a thin substrate.